Join Google as an ASIC Design Lead in Machine Learning and Silicon Technology

We're on the lookout for a seasoned ASIC Design Lead who has not only crafted intricate machine learning compute IPs but also exhibits profound leadership capabilities. This exciting opportunity is based in our innovative and forward-looking Devices & Services team.

Minimum Qualifications:

• A Bachelor’s degree in Electrical Engineering, Computer Science, or a comparable discipline coupled with equivalent practical experience.
• At least 10 years of professional experience in RTL design.
• Demonstrated experience leading a team through the full development cycle of SoC subsystems, like Neural Processing Units or GPUs, from concept to production.
• Proven ability to work cross-functionally with teams in Software, Architecture, Design Verification, and SoC integration.

Preferred Qualifications:

• An advanced degree, such as a Master's or PhD, in Computer Science, Electrical Engineering, or a related field.
• Broad experience spanning architecture, micro-architecture, design verification, implementation, emulation, and silicon bring-up.
• Experience improving productivity with Design Verification and integration teams through innovative methodologies.
• Experience with high-performance compute IPs like GPUs, DSPs, or Neural Processing Units.

About the Job:

At Google, the size and complexity of the computational challenges we face mean that off-the-shelf hardware solutions just don’t cut it. That’s why we build it ourselves. As a Hardware Engineer, you will not only design but also build the systems at the core of the world’s largest and most potent computing infrastructure. You will see your designs through from the earliest stages of circuit design to global-scale production, directly shaping the technology that powers Google’s data centers and impacts millions of our users.

Responsibilities:

• Lead and manage a team of talented RTL engineers, guiding the design of sophisticated machine learning compute IPs.
• Ensure close collaboration with the Verification and Silicon Validation teams to confirm functionality and performance.
• Influence the synthesis, timing closure, and physical design of digital blocks.
• Drive your team towards achieving exceptional Power Performance Area (PPA) benchmarks vital for a variety of SoCs.
• Collaborate with SoC Design and multiple cross-functional teams to ensure successful IP design implementation throughout all production phases up to tape-out.

Join Google, where we don’t just accept difference—we celebrate it, we support it, and we thrive on it for the benefit of our employees, our products, and our community. Apply today and transform the future of technology.