Job Opportunity: RTL Design Engineer, Security at Google

Minimum Qualifications

- 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC).

- Experience in scripting languages such as Perl or Python.

- Experience in area, power, and performance optimization.

Preferred Qualifications

- Master’s degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.

- Experience in the design and development of security blocks or crypto blocks.

About The Job

Our computational challenges are so big, complex, and unique that we can't simply purchase off-the-shelf hardware; we need to create it ourselves. Your team will design and build the hardware, software, and networking technologies that power all of Google's services. As a Hardware Engineer, you will be responsible for designing and building the systems that form the backbone of the world's largest and most powerful computing infrastructure. You will engage in activities ranging from the lowest levels of circuit design to large system design, and guide these systems all the way through to high-volume manufacturing. Your work at Google has the potential to shape the technology that goes into our cutting-edge data centers, impacting millions of Google users worldwide.

In this role, you will be responsible for the Register-Transfer Level (RTL) design and development of security IP and subsystems. This encompasses microarchitecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews, and closure for high-quality and optimized security designs.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, software, and hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, aiming to improve people’s lives through technology.

Responsibilities

- Participate in test planning and coverage analysis.

- Develop RTL implementations that meet power, performance, and area goals.

- Engage in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA) and silicon bring-up.

- Perform Verilog/SystemVerilog RTL coding, functional and performance simulation debug, and Lint/CDC/FV/UPF checks.

- Create tools/scripts to automate tasks and track progress.

Join us at Google and leverage your skills in a challenging yet rewarding environment. Together, we can develop technologies that make a real difference in the world.

Company Name: Google

Job Title: RTL Design Engineer, Security