Job Opportunity: RTL Design Manager for CPU and Silicon at Google

Company Name: Google

Job Title: RTL Design Manager, CPU, Silicon

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
• 4 years of experience in people management and employee development.
• Experience with CPU or AI accelerator integration with SOC.
• Proficiency in RTL language (System Verilog) and related design processes such as Lint and UPF.

Preferred Qualifications:

• PhD in Electrical Engineering or Computer Science.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture.
• Comprehensive experience in SOC design, architecture, and integration.

About the Job:

At Google, our computational challenges are immense, intricate, and unparalleled, requiring us to design our own hardware. As a Hardware Engineer, you will be part of a team that creates the hardware, software, and networking technologies powering Google’s extensive services.

In your role, you will be responsible for designing and building systems central to one of the world’s largest computing infrastructures. Starting from circuit design and extending to expansive system design, you will see these projects through to high-volume manufacturing. Your contributions can influence the machinery used in our cutting-edge data centers, impacting millions of Google users worldwide.

Leveraging both your technical skills and leadership abilities, you'll spearhead research projects across various expertise areas within data center facilities, while overseeing a team responsible for equipment installation, troubleshooting, and debugging.

Key Responsibilities:

• Participate in the development of CPU subsystems.
• Design front-end CPU subsystems with a focus on microarchitecture and RTL design for next-generation CPUs.
• Propose performance-enhancing microarchitecture features and collaborate with Software, Architecture, and Performance teams for trade-off studies.
• Communicate the trade-offs of microarchitecture enhancements, delivering designs that meet PPA goals with production quality.
• Coordinate with the Verification team to ensure high-quality designs and work with physical design and power teams to meet frequency, power, and area goals.
• Stay updated on modern techniques, adapt them into design constructs and languages, and participate in performance evaluation efforts.