Join Google as an ASIC Power Architect, Silicon

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in ASIC power management or low power design/methodology.
• Experience with ASIC low power flows and power management concepts.

Preferred Qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience with areas such as ASIC power modeling and estimation, defining power targets, power management IP and sensors, peak power management/detection/mitigation, in-rush current, adaptive clock distribution, techniques for power/voltage domains design, and competitive power analysis.
• Experience with low power architectures and power optimization techniques including multi Vth/power/voltage domain design, clock gating, power gating, and Dynamic Voltage Frequency Scaling (DVFS, AVS).
• Familiarity with PMIC, SMPS, LDO, and power delivery networks.

About the Job

Are you ready to tackle computational challenges that are too big, complex, and unique for off-the-shelf hardware? At Google, you will design and build the hardware, software, and networking technologies powering all our services. As a Hardware Engineer, you will contribute to the creation of systems at the heart of the world’s largest and most powerful computing infrastructure. From the lowest levels of circuit design to massive system creation, you will see your designs come to life and go into high volume manufacturing. Your technical expertise will lead projects across multiple domains within our data center facilities, including construction, equipment installation, and troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team integrates the best of Google AI, Software, and Hardware to create groundbreaking experiences. We research, design, and develop new technologies and hardware aimed at making computing faster, seamless, and more powerful—improving people's lives through innovative technology.

Responsibilities

• Define and drive low power solutions for Google SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
• Create use case workload and data flow models for Day of Use (DoU) power evaluation and drive power and performance optimizations across SoC generations.
• Define performance/power KPIs and SoC/IP-level performance/power targets, guide architecture and design to achieve lower power benchmarks, perform power roll-ups, and monitor power throughout the design cycle.
• Propose and drive power optimizations throughout the design process from concept to mass production.
• Conduct power-performance trade-off analysis for engineering reviews and product roadmap decisions.

Join us at Google and be a key player in shaping the future of computing. Make an impact with your expertise by developing cutting-edge technologies that power millions of Google users worldwide.

Additional Information:

Company Name: Google
Job Title: ASIC Power Architect, Silicon