Job Opportunity: Chassis Power Architect, Silicon

Join our team at Google as a Chassis Power Architect within the Silicon Platform IP division. If you're an expert in power optimization and want to work on groundbreaking technologies, this opportunity is for you. Read on to learn more about the role, qualifications, and benefits.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 6 years of experience in power optimization workflow.
• Experience with silicon power optimization methods and techniques.
• Experience with power management IPs.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, specializing in computer architecture.
• Experience in post-silicon power calibrations and debug.
• Experience in low power design including UPF/CPF, multi-voltage domains, power gating, and on-chip power management IP design.
• Proficiency in using Electronic Design Automation (EDA) tools like Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
• Experience in the design and analysis of full chip power, with an understanding of clock, reset, and power sequencing interactions.
• Understanding of ASIC design flows and methodologies.

About the Job

Google faces unique and complex computational challenges that require bespoke hardware solutions. As a Hardware Engineer, you will design and build the critical systems that power one of the largest and most sophisticated computing infrastructures in the world. From the smallest circuit design to comprehensive system designs, your work will affect millions of users globally.

Utilizing your technical acumen and leadership skills, you will spearhead research projects across multiple areas, overseeing teams that manage equipment installation, troubleshooting, and debugging in data center facilities.

Role and Responsibilities

• Collaborate with hardware architects and design engineers to drive chassis power optimization in advanced technology nodes.
• Define power optimization methods and chart power roadmaps for chassis IPs.
• Propose power optimization plans in coordination with cross-functional teams.
• Guide pre-silicon power modeling and post-silicon power correlation efforts.
• Interface with system and chipset power architects to develop power planning and management strategies.
• Focus on next-generation chassis power architecture, microarchitecture, and power vs. performance trade-offs.

Google's Mission and Team

Google aims to organize the world’s information, making it universally accessible and useful. Our team integrates AI, software, and hardware innovations to deliver exceptional user experiences. By researching, designing, and developing new technologies, we strive to make computing faster, more seamless, and powerful, ultimately enhancing people's lives through technology.

Compensation and Benefits

The US base salary range for this full-time position is $150,000-$223,000, plus bonuses, equity, and comprehensive benefits. Salary ranges are determined by role, level, and location. Your specific compensation will be influenced by your work location, job-related skills, experience, and relevant education or training. Your recruiter can provide more details regarding the salary range for your preferred location during the hiring process.

Please note that the salary range only includes the base salary and does not encompass bonuses, equity, or additional benefits. For more information on Google's benefits, please visit our benefits page.

Apply Today

If you are ready to take on this exciting challenge and help us build the future of computing, we encourage you to apply for the Chassis Power Architect, Silicon position at Google today.