FPGA Development Tools Engineer - Job Opportunity in Toronto, Canada

Company: Intel

Job Responsibilities

In Q4 2023, Intel announced that Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel. This position is aligned with that standalone business strategy and is expected to transition into a separate company in the future.

The Quartus Compiler Placer Team in Toronto specializes in developing cutting-edge algorithms in C++ for mapping digital circuits to our FPGA devices. We utilize various optimization algorithms and AI techniques to tackle the placement problem, including:

• Analytical placement methods for global placement optimization
• Annealing algorithms for detailed placement refinement
• Network flow solvers for hard placement constraints

The primary aim of the placer is to generate near-optimal results for finding a physical location for every block in the user’s design with reasonable runtime while optimizing the timing of the design for achieving timing closure for their target design frequency.

This role includes research, design, development, and optimization of software tools that enable the use of Field Programmable Gate Arrays (FPGA). You will leverage your strong knowledge of FPGA hardware, logic design, board design, and semiconductor devices to accelerate designs in domains such as deep learning, DSP algorithms, or data analytics.

Qualifications

Minimum Education Requirements

• BS degree with 10+ years of experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• MS with 8+ years of industry experience, or PhD with 6+ years of industry software experience

Minimum Qualifications

• Minimum of 8 years of C++ programming in a Linux/Unix environment
• Minimum of 6 years of experience with FPGA or ASIC development flows

Preferred Qualifications

• Experience in C++ coding and development of high-performance parallel software systems
• Experience working in modern, large-scale modular code bases
• Experience developing EDA/CAD placement optimization algorithms for FPGAs or ASICs
• Experience with FPGA placement optimization approaches for analytical placement, clustering, or detailed placement
• 2+ years' experience with Altera Quartus or Xilinx Vivado
• Experience with scripting languages such as Python, Perl, or TCL

Job Details

Job Type: Experienced Hire

Shift: Shift 1 (Canada)

Primary Location: Toronto, Canada

Additional Locations: N/A

Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG creates market-leading programmable logic devices that offer enhanced capabilities over current solutions. By combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities, customers can develop next-generation electronic systems with unmatched performance and power efficiency.

PSG prides itself on creating an energetic and innovative work environment. We believe our success is directly linked to our employee's growth and satisfaction. PSG is committed to a flexible and collaborative work environment that enables employees to reach their full potential.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Additional Information

Position of Trust: N/A

Annual Salary Range: CAD 150,740.00 - 226,140.00 (Dependent on location and experience)

Work Model: This role requires an on-site presence.

Accommodation

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities.