Platform Memory Controller Architect, Silicon - Google

About the Job

At Google, our computational challenges are so big, complex, and unique that off-the-shelf hardware isn't sufficient. We design and create the hardware, software, and networking technologies that drive the services used by millions globally. As a Hardware Engineer specializing in the heart of our advanced computing infrastructure, you will design, develop, and manufacture systems from the lowest levels of circuit design to large-scale systems that go into high-volume production in our data centers.

Leveraging your technical and leadership skills, you will lead comprehensive research projects across multiple areas in data center facilities. You'll manage a team responsible for equipment installation, troubleshooting, and debugging, ensuring efficient and effective operations. Your work can shape the future of our cutting-edge data centers, directly impacting millions of users.

Google's mission is to organize the world’s information and make it universally accessible and useful. Our team marries Google AI, Software, and Hardware to create transformative experiences. We strive to research, design, and develop technologies and hardware that make computing faster, seamless, and more powerful, enhancing people’s lives through innovation.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience in memory controller architecture/micro-architecture.
• Experience in ASIC architecture performance analysis, tools, and simulators at different abstraction levels (e.g., Cycle Accurate, TLM, or Functional).

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with coding in C/C++/Python.
• Experience working with third-party vendor solutions.
• Experience designing, implementing, or validating RTL for Fabric, MMUs, Caches, or memory controllers.
• Knowledge of HDL languages, such as System Verilog, Verilog.
• Understanding of coherent interconnects, caches, or memory systems.

Responsibilities

• Explore and evaluate architectural design choices for DRAM memory controller and the entire memory system.
• Build hardware architectural specifications for next-generation memory controller IP.
• Collaborate with other hardware and software architects to understand and enhance architecture.
• Develop C-models, simulate, and analyze performance and power trade-offs.
• Work with hardware design, verification, emulation, and validation teams to develop and test hardware architecture.

Additional Information

Company Name: Google
Job Title: Platform Memory Controller Architect, Silicon