Integration Methodology and Flow Physical Design Engineer, Silicon at Google

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with SoC Integration focused on low power design.
• Experience with new process technology-based SoC integration flow development and tape-out.
• Proficiency in scripting languages such as Python, Bash, and Tcl for workflow automation and data visualization.
• Experience with physical design flow development and design closure for multiple ASIC/SoCs.

Preferred Qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• Experience in System-on-a-Chip (SoC) integration, including 2.5D and 3D Integrated Circuit integration and sign-off.
• Experience in the extraction of ASIC design parameters, Quality of Results (QoR) metrics, and trend analysis.
• Experience in co-optimization to enable schedule-sensitive development considering block complexity, power domains, clocking, congestion, etc.

About the Job:

At Google, our computational challenges are vast, complex, and unique—requiring custom-built solutions that can't be sourced off-the-shelf. As a Hardware Engineer, you will design and build the systems powering the world’s largest and most advanced computing infrastructure. From circuit design to large system design, and manufacturing at scale, your work will impact millions of Google users. You will leverage your technical expertise to lead projects across multiple engineering domains within data center facilities, including construction and troubleshooting/debugging with vendors.

Google’s mission is to organize the world's information and make it universally accessible and useful. Our team brings together the best of Google AI, software, and hardware to create groundbreaking experiences. We design and develop new technologies and hardware to make computing faster, seamless, and more powerful, improving lives through innovation.

US Base Salary:

The US base salary range for this full-time position is $150,000 - $223,000, plus bonus, equity, and benefits. Salary ranges are determined by role, level, and location, reflecting the minimum and maximum target salaries for the position across all US locations. Your recruiter will discuss the specific salary range for your preferred location during the hiring process. Please note that the listed compensation details are for base salary only and do not include bonus, equity, or benefits.

Learn more about benefits at Google.

Responsibilities:

• Develop, support, and execute SoC integration flow development and execution, including multiple scenarios of Die Size planning, Bump planning, IO and Block placements, Power regions planning, Layout routing planning, and Product Graphics grid with multiple power regions.
• Oversee bump/micro-bump to package integration planning and implementation, incorporating package-driven feedback into high-level design.
• Ensure SoC integration is block-friendly, easy to implement, and meets Power, Performance, and Area (PPA) goals.
• Ensure multiple power domains Electromigration/Voltage (EM/IR) and bump planning meet reliability requirements.
• Own and drive the execution of high-level SoC design and partner with foundries to resolve issues related to new technologies.