Senior Analog Layout Engineer

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Join Apple as a Senior Analog Layout Engineer

Posted: Jun 21, 2024
Weekly Hours: 40
Role Number: 200537002

Join Apple's Silicon Engineering Group (SEG) and be instrumental in crafting the next generation of Apple's system-on-chips (SOCs). Our SOCs, featuring multi-billion transistors, are the core of world-renowned devices like iPhones, iPads, and Macs. We are in search of highly skilled Senior Analog Layout Leads to propel the evolution of Analog/Mixed-Signal (AMS) circuits, including SerDes, PLLs, and sensors.

Job Description

As a Senior Layout Lead, you'll have a critical role in translating design concepts into silicon. Collaborate closely with circuit designers and use advanced tools to craft custom analog designs that optimize Apple's groundbreaking products' performance. In this dynamic and innovative environment, you will continuously learn and work with talented multidisciplinary teams.

This role is ideal for self-motivated engineers passionate about working with cutting-edge technology, seeking to accelerate career growth, and thriving in a results-driven environment. If you're eager to contribute to revolutionary Apple products, this is the place for you. You will have the chance to work on next-generation products, tackle challenges, and broaden your skillset in a dynamic, innovative work culture.

Key Responsibilities

Senior Layout Engineers/Leads are crucial in delivering Analog Mixed-Signal IP within a SOC flow. Key responsibilities include:

  • Developing sophisticated layouts for mixed-signal and analog circuits.
  • Reviewing floorplans and analyzing intricate circuits alongside circuit designers.
  • Running comprehensive sets of design verification tools, planning/scheduling work, and coordinating critical layout tradeoffs.
  • Interpreting LVS, DRC, and ERC reports to ensure layout meets engineering specifications and expectations.

Required Qualifications

  • 10+ years’ experience in analog/mixed-signal layout design, focusing on deep submicron CMOS circuits and at least 3+ years in FinFET technologies.
  • Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python.
  • Proficiency with Machine Learning and AI concepts.
  • Expertise in implementing analog layout designs meeting tight matching, low noise, and low power consumption requirements.
  • Experience with analog and DFM best practices and identifying optimal problem-solving approaches.
  • High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly.
  • Technical understanding of IR drop, RC delay, electromigration, self-heating, and coupling capacitance.
  • Strong skills in interpreting physical verification reports (DRC, ERC, LVS, etc.).
  • Experience using Cadence Virtuoso’s advanced features (XL, EAD, APR, and Constraint Manager).
  • Excellent communication skills and capability to work with cross-functional teams.

Additional Skills (Preferred)

  • Cadence Innovus
  • CAD Automation experience
  • Pcell creation experience

Education & Experience

BSEE, MSEE, or equivalent with 10+ years of relevant experience. A focus on Mixed-Signal and RF Integrated Circuits is advantageous.

Equal Opportunity and Diversity at Apple

Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to provide employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. Learn more about your

Pay & Benefits

At Apple, base pay is a part of our total compensation package, determined within a range. For this role, the base pay ranges from $152,400 to $268,200, depending on your skills, qualifications, experience, and location.

Apple employees can also become Apple shareholders through our Employee Stock Purchase Plan, receive discretionary restricted stock unit awards, and enjoy