Join NVIDIA as a Senior ASIC Physical Design and Timing Engineer

Are you a skilled and motivated ASIC Physical Design and Timing Engineer looking to challenge yourself and contribute to groundbreaking innovations? NVIDIA, a company that has been continuously reinventing itself for over two decades, invites you to be a part of our dynamic and growing team.

About NVIDIA

NVIDIA's pioneering invention of the GPU in 1999 launched the PC gaming revolution, redefined modern computer graphics, and transformed parallel computing. Recently, our GPU deep learning technology has driven the rise of modern AI, ushering in the next computing era. At NVIDIA, we are constantly adapting and evolving, taking on new opportunities that matter to the world. Our mission is to amplify human inventiveness and intelligence.

What You’ll Be Doing

• Drive the physical design and timing of high-frequency, low-power CPU, GPU, DPU, and SoCs at various levels (block, cluster, and full chip).
• Assist in the implementation of frontend and backend processes from RTL to GDS2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Collaborate with cross-functional teams to drive project success.
• Apply your expertise to enhance convergence flows in collaboration with the Methodology Team.

What We Need to See

• BS in Electrical or Computer Engineering with 5+ years of experience, or MS with 2+ years of experience in Synthesis and Timing.
• Hands-on experience with full-chip or sub-chip Static Timing Analysis (STA), timing constraints generation, and timing convergence.
• Expertise in resolving crosstalk delay, noise glitch, and electrical/manufacturing rule issues in deep-submicron processes.
• Proficiency in physical design and optimization techniques, such as placement, routing, cell sizing, buffering, logic restructuring, and ECOs.
• Familiarity with logic synthesis and equivalence checking/formal verification.
• Proficient in industry-standard EDA tools and programming/scripting languages (e.g., Perl, Tcl, Python).

Ways to Stand Out from the Crowd

• Experience with high-performance designs, such as CPU, GPU, or network processor implementation and timing convergence.
• Strong understanding of hardware architecture and skills in RTL/logic design for timing closure.
• Knowledge of DFT logic and experience with DFT timing closure for various modes (e.g., scan shift and capture, transition faults, BIST).
• Understanding deep sub-micron technology and process variations, including modeling and convergence considerations.
• Experience with circuits, SPICE simulations, transistor-level STA, and methodology/flow development/automation.

Compensation and Benefits

The base salary range for this role is $128,000 - $258,750, based on your location, experience, and the pay of employees in similar positions. In addition to a competitive base salary, you will be eligible for equity and benefits.

Application and Diversity Commitment

NVIDIA accepts applications on an ongoing basis and is committed to creating a diverse work environment. We are proud to be an equal opportunity employer and value diversity in our current and future employees. We do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

Company Name: NVIDIA

Job Title: Senior ASIC Physical Design and Timing Engineer

Join NVIDIA today and become part of a team that is shaping the future of technology!