Lead SoC Architect, NPU AI/ML

Lab Overview:

The vision of the Samsung SOC Lab is to offer innovative SoC architecture, bus/memory subsystems, multimedia subsystems, and critical IP blocks for future Samsung Galaxy products (smartphones, tablets, and future devices). We are shaping the high-performance SoC architecture development for various Galaxy device lineups. This lab works in conjunction with Samsung's strategic SoC partners, Samsung MX head office team, and core R&D teams worldwide to innovate and recreate technology that will positively affect millions of people around the world via the Galaxy flagship products.

Position Summary:

We are seeking a Lead SOC Architect, NPU for next-generation SOCs. This is a highly visible hands-on role leading individual and team contributions to NPU [AI/ML] sub-system architecture, interface, performance, and power trade-offs.

Position Responsibilities:

• Direct the development of innovative NPU Architectural and microarchitectural features to enhance PPA (Performance, Power and Area) on various targeted workloads in next-generation SOCs.
• Identify and deliver NPU subsystem architecture proposals for products in new and existing markets.
• Show good knowledge of existing AI/ML algorithms used in Smartphone, AR/VR/XR applications.
• Evaluate architecture proposal benefits in collaboration with a team of SoC Architects and communicate the results to related engineering audiences (SW, HW, Architecture, Leadership).
• Carry out high-level performance modeling/simulation and analysis of NPU features, applications, benchmarks, and complex use cases.
• Direct, work hands-on, and coordinate performance modeling, and studies to support the inclusion of these features in the next-generation SoC.
• Deliver architecture/microarchitecture proposals and specifications to the design team and explain them effectively to audiences ranging from hardware & software engineers to architecture community peers, and technology leadership.
• Collaborate with silicon and platform set-up and product teams to verify and debug the proposal and its delivered performance.
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations.

Required Skills:

• A BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience.
• More than 15 years of experience in SOC or ASIC design and architecture.
• Direct experience (> 7 years) in NPU subsystem architecture or microarchitecture is required.
• High proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around NPU IPs.
• The ability to leverage existing simulation capabilities [GEM5, FastSIM, Platform Architect] or to create new simulation capabilities when necessary.
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), GPU architecture, and new development.
• Leadership across hardware, software, and platform groups to align all parties to a common vision.